Having a cache block of 4words, having one-word-wide bank of DRAMs and miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be

Having a cache block of 4words, having one-word-wide bank of DRAMs and miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be
  • A. 0.2
  • B. 0.25
  • C. 0.75
  • D. 1.5
  • Correct Answer: Option B
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