Flip-Flops

mcqspedia.com has 35 Question/Answers about Topic Flip-Flops

To completely load and then unload an 8-bit register requires how many clock pulses?

To completely load and then unload an 8-bit register requires how many clock pulses?
  • A. 2
  • B. 4
  • C. 8
  • D. 16
  • Correct Answer: Option D

What is the difference between the 7476 and the 74LS76?

What is the difference between the 7476 and the 74LS76?
  • A. the 7476 is master-slave, the 74LS76 is master-slave
  • B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
  • C. the 7476 is edge-triggered, the 74LS76 is master-slave
  • D. the 7476 is master-slave, the 74LS76 is edge-triggered
  • Correct Answer: Option D

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
  • A. 16
  • B. 8
  • C. 4
  • D. 2
  • Correct Answer: Option B

If an input is activated by a signal transition, it is ________.

If an input is activated by a signal transition, it is ________.
  • A. edge-triggered
  • B. toggle triggered
  • C. clock triggered
  • D. noise triggered
  • Correct Answer: Option A

On a master-slave flip-flop, when is the master enabled?

On a master-slave flip-flop, when is the master enabled?
  • A. when the gate is LOW
  • B. when the gate is HIGH
  • C. both of the above
  • D. neither of the above
  • Correct Answer: Option B

How is a J-K flip-flop made to toggle?

How is a J-K flip-flop made to toggle?
  • A. J = 0, K = 0
  • B. J = 1, K = 0
  • C. J = 0, K = 1
  • D. J = 1, K = 1
  • Correct Answer: Option D

On a J-K flip-flop, when is the flip-flop in a hold condition?

On a J-K flip-flop, when is the flip-flop in a hold condition?
  • A. J = 0, K = 0
  • B. J = 1, K = 0
  • C. J = 0, K = 1
  • D. J = 1, K = 1
  • Correct Answer: Option A

The phenomenon of interpreting unwanted signals on J and K while Cp

The phenomenon of interpreting unwanted signals on J and K while Cp
  • A. parity error checking
  • B. ones catching
  • C. digital discrimination
  • D. digital filtering
  • Correct Answer: Option B

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
  • A. clock is LOW
  • B. slave is transferring
  • C. flip-flop is reset
  • D. clock is HIGH
  • Correct Answer: Option D

How many flip-flops are in the 7475 IC?

How many flip-flops are in the 7475 IC?
  • A. 1
  • B. 2
  • C. 4
  • D. 8
  • Correct Answer: Option C

Which of the following describes the operation of a positive edge-triggered D flip-flop?

Which of the following describes the operation of a positive edge-triggered D flip-flop?
  • A. If both inputs are HIGH, the output will toggle.
  • B. The output will follow the input on the leading edge of the clock.
  • C. When both inputs are LOW, an invalid state exists.
  • D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
  • Correct Answer: Option B

Edge-triggered flip-flops must have:

Edge-triggered flip-flops must have:
  • A. very fast response times
  • B. at least two inputs to handle rising and falling edges
  • C. positive edge-detection circuits
  • D. negative edge-detection circuits
  • Correct Answer: Option C

Which of the following is correct for a gated D flip-flop?

Which of the following is correct for a gated D flip-flop?
  • A. The output toggles if one of the inputs is held HIGH.
  • B. Only one of the inputs can be HIGH at a time.
  • C. The output complement follows the input when enabled.
  • D. Q output follows the input D when the enable is HIGH.
  • Correct Answer: Option D

The output of a gated S-R flip-flop changes only if the:

The output of a gated S-R flip-flop changes only if the:
  • A. flip-flop is set
  • B. control input data has changed
  • C. flip-flop is reset
  • D. input data has no change
  • Correct Answer: Option B

What is the hold condition of a flip-flop?

What is the hold condition of a flip-flop?
  • A. both S and R inputs activated
  • B. no active S or R input
  • C. only S is active
  • D. only R is active
  • Correct Answer: Option B

For an S-R flip-flop to be set or reset, the respective input must be:

For an S-R flip-flop to be set or reset, the respective input must be:
  • A. installed with steering diodes
  • B. in parallel with a limiting resistor
  • C. LOW
  • D. HIGH
  • Correct Answer: Option D

If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?

If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
  • A. No change will occur in the output.
  • B. An invalid state will exist.
  • C. The output will toggle.
  • D. The output will reset.
  • Correct Answer: Option A

Most people would prefer to use ________ over HDL.

Most people would prefer to use ________ over HDL.
  • A. graphic descriptions
  • B. functions
  • C. VHDL
  • D. AHDL
  • Correct Answer: Option A

In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.

In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.
  • A. function
  • B. signal
  • C. semicolon
  • D. colon
  • Correct Answer: Option D

Regardless of whether you develop a description in AHDL or VHDL, the circuit’s proper operation can be verified using a ________.

Regardless of whether you develop a description in AHDL or VHDL, the circuit’s proper operation can be verified using a ________.
  • A. PROCESS
  • B. computer
  • C. simulator
  • D. primitive library
  • Correct Answer: Option C
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