Digital Design

mcqspedia.com has 20 Question/Answers about Topic Digital Design

The output of a standard TTL NAND gate is used to pull an LED indicator LOW. The LED is in series with a 470- resistor. What is the current in the circuit when the LED is on?

The output of a standard TTL NAND gate is used to pull an LED indicator LOW. The LED is in series with a 470- resistor. What is the current in the circuit when the LED is on?
  • A. 7.02 mA
  • B. 8.51 mA
  • C. 10.63 mA
  • D. 5.32 mA
  • Correct Answer: Option A

Why should a LED be pulled LOW from a logic gate rather than pulled HIGH?

Why should a LED be pulled LOW from a logic gate rather than pulled HIGH?
  • A. LOW-level current is smaller.
  • B. LOW-level current is larger.
  • C. HIGH-level current is larger.
  • D. LOW-level current is smaller and HIGH-level current is larger.
  • Correct Answer: Option B

Why is the Schmitt trigger needed in the 60-Hz TTL-level clock pulse generator?

Why is the Schmitt trigger needed in the 60-Hz TTL-level clock pulse generator?
  • A. to provide a triangle wave
  • B. to provide a sine wave
  • C. to provide a rounded pulse waveform
  • D. to provide a sharp pulse waveform
  • Correct Answer: Option D

What would be the output voltage of a 7814 voltage regulator?

What would be the output voltage of a 7814 voltage regulator?
  • A. –14 V dc
  • B. +14 V dc
  • C. –8 V dc
  • D. +8 V dc
  • Correct Answer: Option B

A 0.01-F capacitor is recommended by TTL manufacturers for ________ the power supply.

A 0.01-F capacitor is recommended by TTL manufacturers for ________ the power supply.
  • A. decoupling
  • B. filtering
  • C. rectifying
  • D. grounding
  • Correct Answer: Option A

The main concern when using a pull-down resistor is:

The main concern when using a pull-down resistor is:
  • A. the low power dissipation of the resistor
  • B. it will keep a floating terminal LOW
  • C. the high power dissipation of the resistor
  • D. it will cause false triggering
  • Correct Answer: Option C

The purpose of a pull-up resistor is to keep a terminal at a ________ level when it would normally be at a ________ level.

The purpose of a pull-up resistor is to keep a terminal at a ________ level when it would normally be at a ________ level.
  • A. LOW, float
  • B. HIGH, float
  • C. clock, float
  • D. pulsed, float
  • Correct Answer: Option B

One example for the use of a Schmitt trigger is as a(n):

One example for the use of a Schmitt trigger is as a(n):
  • A. switch debouncer
  • B. racer
  • C. astable oscillator
  • D. transition pulse generator
  • Correct Answer: Option A

A Schmitt trigger has VT+

A Schmitt trigger has VT+
  • A. 0.4 volt
  • B. 0.6 volt
  • C. 0.8 volt
  • D. 1.2 volts
  • Correct Answer: Option C

A Schmitt trigger:

A Schmitt trigger:
  • A. has two trip points
  • B. is a zero crossing detector
  • C. has positive feedback
  • D. has two trip points and positive feedback
  • Correct Answer: Option D

The ________ circuit overcomes the problem of switching caused by jitter on the inputs.

The ________ circuit overcomes the problem of switching caused by jitter on the inputs.
  • A. astable multivibrator
  • B. monostable multivibrator
  • C. bistable multivibrator
  • D. Schmitt trigger
  • Correct Answer: Option D

A settable flip-flop’s normal starting state when power is first applied to a circuit is always the ________ state.

A settable flip-flop’s normal starting state when power is first applied to a circuit is always the ________ state.
  • A. reset
  • B. set
  • C. toggle
  • D. dual
  • Correct Answer: Option B

In the automatic reset circuit for a flip-flop, how long does it take the capacitor to completely charge?

In the automatic reset circuit for a flip-flop, how long does it take the capacitor to completely charge?
  • A. 1 time constant (RC)
  • B. 2 time constants (RC)
  • C. 5 time constants (RC)
  • D. 10 time constants (RC)
  • Correct Answer: Option C

How much setup time (ts

How much setup time (ts
  • A. 5 ns
  • B. 10 ns
  • C. 20 ns
  • D. 40 ns
  • Correct Answer: Option C

Why would a delay gate be needed for a digital circuit?

Why would a delay gate be needed for a digital circuit?
  • A. A delay gate is never needed.
  • B. to provide for setup times
  • C. to provide for hold times
  • D. to provide for setup times and hold times
  • Correct Answer: Option D

Look up the propagation delay from the clock to the output for the 7476. Are the HIGH-to-LOW and LOW-to-HIGH propagation delays the same?

Look up the propagation delay from the clock to the output for the 7476. Are the HIGH-to-LOW and LOW-to-HIGH propagation delays the same?
  • A. yes
  • B. no, tPLH = 25 ns, tPHL = 40 ns
  • C. no, tPLH = 40 ns, tPHL = 25 ns
  • D. no, tPHL = 25 ns, tPLH = 40 ns
  • Correct Answer: Option B

When the inputs to a flip-flop are changing at the same time that the active trigger edge of the input clock is making its transition, this condition is called:

When the inputs to a flip-flop are changing at the same time that the active trigger edge of the input clock is making its transition, this condition is called:
  • A. racing
  • B. toggling
  • C. slave loading
  • D. pulse timing
  • Correct Answer: Option A

Which of the following circuit parameters would be most likely to limit the maximum operating frequency of a flip-flop?

Which of the following circuit parameters would be most likely to limit the maximum operating frequency of a flip-flop?
  • A. setup and hold time
  • B. clock pulse HIGH and LOW time
  • C. propagation delay time
  • D. clock transition time
  • Correct Answer: Option C

Setup time specifies:

Setup time specifies:
  • A. the minimum time the control levels need to be maintained on the inputs prior to the triggering edge of the clock in order to be reliably clocked into the flip-flop
  • B. the maximum time interval required for the control levels to remain on the inputs before the triggered edge of the clock in order for the data to be reliably clocked out of the flip-flop
  • C. how long the operator has to get the flip-flop running before the maximum power level is exceeded
  • D. how long it takes the output to change states after the clock has transitioned
  • Correct Answer: Option A

What is the major advantage of the J-K flip-flop over the S-R flip-flop?

What is the major advantage of the J-K flip-flop over the S-R flip-flop?
  • A. The J-K flip-flop is much faster.
  • B. The J-K flip-flop does not have propagation delay problems.
  • C. The J-K flip-flop has a toggle state.
  • D. The J-K flip-flop has two outputs.
  • Correct Answer: Option C