design of memory hierarchies

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Instruction miss which is serviced by main memory, has total latency, approximately of

Instruction miss which is serviced by main memory, has total latency, approximately of
  • A. 35 processor cycles
  • B. 40 processor cycles
  • C. 42 processor cycles
  • D. 45 processor cycles
  • Correct Answer: Option A

If L2 cache is missed and L3 cache is accessed. For a 4-core i7, which is having 8MB L3, index size will be

If L2 cache is missed and L3 cache is accessed. For a 4-core i7, which is having 8MB L3, index size will be
  • A. 2^9
  • B. 2^13
  • C. 2^15
  • D. 2^17
  • Correct Answer: Option B

Index of instruction cache is

Index of instruction cache is
  • A. 2Index= Cache size- Block size
  • B. 2Index= Cache size/ Block size + Set associativity
  • C. 2Index= Cache size+ Block size
  • D. 2Index= Cache size/ Block size
  • Correct Answer: Option D

When cache having size 32k, block-size 64 and set associativity 4, will have cache index of

When cache having size 32k, block-size 64 and set associativity 4, will have cache index of
  • A. 2^2
  • B. 2^5
  • C. 2^7
  • D. 2^9
  • Correct Answer: Option C

Cortex-A8 known as configurable core, which supports computer instruction set architecture of

Cortex-A8 known as configurable core, which supports computer instruction set architecture of
  • A. ARMv6
  • B. ARMv7
  • C. ARMv8
  • D. ARMv9
  • Correct Answer: Option B