caches and cache types

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Having a cache block of 4words, having one-word-wide bank of DRAMs and miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be

Having a cache block of 4words, having one-word-wide bank of DRAMs and miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be
  • A. 0.2
  • B. 0.25
  • C. 0.75
  • D. 1.5
  • Correct Answer: Option B

Cache having 64 blocks and a block-size of 16 bytes, will have block-no for address 1200 map to

Cache having 64 blocks and a block-size of 16 bytes, will have block-no for address 1200 map to
  • A. 75 modulo 64
  • B. 75 modulo 60
  • C. 70 modulo 64
  • D. 72 modulo 64
  • Correct Answer: Option A

A queue holding data while data are waiting to be written in memory, is known as

A queue holding data while data are waiting to be written in memory, is known as
  • A. Read buffer
  • B. Queue buffer
  • C. Write buffer
  • D. Data buffer
  • Correct Answer: Option C

Levels between CPU and main memory were given a name of

Levels between CPU and main memory were given a name of
  • A. Hit time
  • B. Miss rate
  • C. Locality in time
  • D. Cache
  • Correct Answer: Option D

In a direct-mapped cache of eight words (1)10 (00001two) and (29)10 (11101two) map to locations

In a direct-mapped cache of eight words (1)10 (00001two) and (29)10 (11101two) map to locations
  • A. 0ten (001two) and 5ten (101two)
  • B. 1ten (001two) and 4ten (101two)
  • C. 1ten (001two) and 5ten (101two)
  • D. 1ten (001two) and 6ten (101two)
  • Correct Answer: Option C